The invention relates to a semiconductor device having a semiconductor body including at least one field effect transistor having surface-adjoining source and drain zones and a channel region which is bounded by the source and drain zones and adjoins the surface and which has a first channel zone adjoining the source zone and a second channel zone adjoining the drain zone, a first gate electrode part extending from the source zone above the first channel zone, and a second gate electrode part extending above the second channel zone as far as the drain zone, the first and second gate electrode parts together covering substantially the whole channel region and being separated from the channel region by a blocking layer.
The blocking layer may be constituted by a layer of electrically insulating material, by a rectifying metal/semiconductor junction ("Schottky" junction) or by a pn junction, as far as these junctions are normally connected in the reverse direction. In the two last-mentioned cases, the designations "MESFET" (Metal Schottky Field Effect Transistor) are used.
A semiconductor device of the kind described is known from the article of Rodgers et al in I.E.E.E. journal of Solid State Circuits, Volume SC 10, October 1975, p. 322-331. This article describes a field effect transistor of the so-called D-MOST type. The first channel zone is then constituted by the laterally diffused channel zone adjoining the source zone and the second channel zone is constituted by the part of the substrate located between the first channel zone and the drain zone (the "drift region"). The first and second gate electrode parts constitute one coherent gate electrode.
Another example of such a device is a field effect transistor having two separated insulated gate electrodes, as described in the article of Barsain in I.E.E.E. Transactions on Electron Devices, Volume ED 28, May 1981 p. 523-534.
Insulated gate field effect transistors are generally designated by the abbreviation "MOST" (Metal Oxide-Semiconductor Transistor) or more correctly and more generally by the abbreviation "IGFET" (Insulated Gate Field Effect Transistor). These abbreviations will also be used in the present application.
When using field effect transistors, a very important property is the so-called linearity of the transistor, that is to say the extent to which the mutual conductance ##EQU1## (where I.sub.D is the drain current, V.sub.g is the effective gate electrode voltage and V.sub.DS is the voltage between source and drain zone) is constant with varying gate voltage. In addition to satisfactory high-frequency behavior and high mutual conductance, good linearity is most desirable.
In this application the term "effective gate voltage V.sub.g " is to be understood to mean the actual voltage at the first gate electrode part with respect to the source zone minus the threshold voltage with respect to the first channel zone.
It is known that a field effect transistor has better linearity as the channel is made shorter, in order to obtain the desired linearity in combination with favorable high-frequency properties and a high mutual conductance, however, a very short channel of at most 1 um is required. Under given circumstances, this may give rise to technological problems.
In a field effect transistor having two insulated gates of the ordinary type, as described in the last-mentioned publication, the mutual conductance as a function of the effective gate voltage V.sub.g1 at the first gate electrode (with constant drain voltage and a constant voltage difference between the gate electrodes) has a maximum value at a given limit value V.sub.gm of the gate voltage V.sub.g1. With a further increase of the gate voltage, the mutual conductance decreases and then slowly increases again, as can be seen in FIG. 14 of the publication in I.E.E.E. Trans. El. Dev., ED 28, p. 523-534. The limit value V.sub.gm is determined inter alia by the ratio L.sub.1 /L.sub.2 between the lengths L.sub.1 and L.sub.2 of the first and second gate electrode parts, respectively, in this case the separated gate electrodes.
The same form of g.sub.m -V.sub.g characteristic is also obtained with a so-called D-MOS transistor as described in the first-mentioned publication in the I.E.E.E. Journal of Solid State Circuits, SC 10 (1975), p. 322-330, in which both the source zone and a first highly doped channel zone of the opposite conductivity type are formed by doping via the same mask opening. The length of the first channel zone is then determined by the difference in lateral diffusion of the two dopants and the second channel zone (the "drift region") is constituted by a part of the semiconductor layer, in which the first channel zone and the source and drain zones are provided. Such a D-MOST can be considered as a MOS transistor having two consecutively arranged and interconnected gate electrodes, one above each channel zone, which have different threshold voltages due to the difference in surface doping of the two channel zones.
The "peak" in the g.sub.m -V.sub.g characteristic occurring in the above cases forms a generally undesirable irregularity, which limits the part of the characteristic in which the linearity is sufficiently high.